module lib1(in1, in2, in3, in4, out);
  input [7:0] in1;
  input [7:0] in2;
  input [7:0] in3;
  input [7:0] in4;
  output [9:0] out;
  assign out = in1 + in2 + in3 + in4;
endmodule

module lib2(in1, in2, in3, in4, out);
  input [7:0] in1;
  input [7:0] in2;
  input [7:0] in3;
  input [7:0] in4;
  output [9:0] out;
  assign out = in1 + in2 + in3 + in4;
endmodule
